/*
 * Copyright (c) 2024 Analog Devices, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_

#define MAX32_DMA_SLOT_MEMTOMEM          0x00U
#define MAX32_DMA_SLOT_SPI_RX            0x01U
#define MAX32_DMA_SLOT_UART_RX           0x04U
#define MAX32_DMA_SLOT_I2C_CONTROLLER_RX 0x07U
#define MAX32_DMA_SLOT_I3C_CONTROLLER_RX 0x07U
#define MAX32_DMA_SLOT_I2C_TARGET_RX     0x08U
#define MAX32_DMA_SLOT_I3C_TARGET_RX     0x08U
#define MAX32_DMA_SLOT_AES_RX            0x10U
#define MAX32_DMA_SLOT_SPI_TX            0x21U
#define MAX32_DMA_SLOT_UART_TX           0x24U
#define MAX32_DMA_SLOT_I2C_CONTROLLER_TX 0x27U
#define MAX32_DMA_SLOT_I3C_CONTROLLER_TX 0x27U
#define MAX32_DMA_SLOT_I2C_TARGET_TX     0x28U
#define MAX32_DMA_SLOT_I3C_TARGET_TX     0x28U
#define MAX32_DMA_SLOT_CRC               0x2CU
#define MAX32_DMA_SLOT_AES_TX            0x30U

#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_ */
